Traditional corner case analysis in semiconductor circuit design typically involves theuse of predetermined semiconductor process parameters, including Fast, Typical, and Slowcorners for PMOS and NMOS devices, frequently yielding overly conservative designs dueto the utilization of fixed, and potentially non-representative, process parameter valuesfor circuit simulations. Identifying the worst cases of circuit FoMs within typical semiconductor process variation ranges presents a considerable challenge, especially given thecomplexities associated with accurately sampling rare semiconductor events. In response,we introduce NPC-NIS, a model specifically developed for estimating rare cases in semiconductor circuit analysis, leveraging a learnable importance sampling strategy. We modelthe distribution of process parameters that exhibit the worst FoMs within a realistic range.This adaptable framework dynamically identifies and addresses rare semiconductor caseswithin typical process variation ranges, enhancing our circuit design optimization capabilities under realistic conditions. Our empirical results validate the effectiveness of the NeuralImportance Sampling (NIS) approach in identifying and mitigating rare semiconductor scenarios, thereby contributing to the development of more robust and reliable semiconductorcircuit designs and connecting traditional semiconductor corner case analysis with realworld semiconductor applications.